CVE-2023-28746

Published: Mar 14, 2024Modified: Jun 17, 2026Deferred

6.5

Vector

CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:N/A:N

Exploitability: 2.0 / Impact: 4.0

Source: secure@intel.com (Secondary)

Description

Information exposure through microarchitectural state after transient execution from some register files for some Intel(R) Atom(R) Processors may allow an authenticated user to potentially enable information disclosure via local access.

Related CWEs

CWE-1342

Information Exposure through Microarchitectural State after Transient Execution

The processor does not properly clear microarchitectural state after incorrect microcode assists or speculative execution, resulting in transient execution.

References (16)

http://www.openwall.com/lists/oss-security/2024/03/12/13

Source: secure@intel.com

https://lists.debian.org/debian-lts-announce/2024/05/msg00003.html

Source: secure@intel.com

https://lists.debian.org/debian-lts-announce/2024/06/msg00017.html

Source: secure@intel.com

https://lists.fedoraproject.org/archives/list/package-announce@lists.fedoraproject.org/message/EIUICU6CVJUIB6BPJ7P5QTPQR5VOBHFK/

Source: secure@intel.com

https://lists.fedoraproject.org/archives/list/package-announce@lists.fedoraproject.org/message/H63LGAQXPEVJOES73U4XK65I6DASOAAG/

Source: secure@intel.com

https://lists.fedoraproject.org/archives/list/package-announce@lists.fedoraproject.org/message/ZON4TLXG7TG4A2XZG563JMVTGQW4SF3A/

Source: secure@intel.com

https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00898.html

Source: secure@intel.com

http://www.openwall.com/lists/oss-security/2024/03/12/13